datasheet low phase noise clock multiplier ics601-21 idt? / ics? low phase noise clock multiplier 1 ics601-21 rev i 031306 description the ics601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. it is ics? lowest phase noise multiplier. using ics? patented analog and digital phase locked loop (pll) techniques, the chip accepts a 10 - 27 mhz crystal or clock input, and produces output clocks up to 220 mhz at 3.3 v. this product is intended for clock generation. it has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. features ? fully integrated pll, no ex ternal loop filter required ? differential 3.3 v lvpecl outputs ? uses fundamental 10 - 27 mhz crystal or clock ? output clocks up to 220 mhz at 3.3 v ? low phase noise: -122 dbc/hz at 10 khz ? low jitter - 15 ps one sigma typ. ? powerdown mode lowers power consumption ? packaged in 16-pin tssop ? advanced, low power, sub-micron cmos process ? operating voltage of 3.3 v ? commercial temperature range available ? available in pb (lead) free package block diagram clk rom based multipliers vco divide x1/iclk x2 crystal or clock input crystal oscillator reference divider phase comparator vdd charge pump loop filter vco s2:0 nclk 4 gnd
ics601-21 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 2 ics601-21 rev i 031306 pin assignment multiplier select table 0 = connect directly to ground 1 = connect directly to vdd pin descriptions 1 2 3 gnd 4 vdd 5 6 gnd 7 8 clk nclk s1 gnd x2 vdd s2 vdd 16 x1 vdd gnd s0 vdd 15 14 13 12 11 10 9 16 pin (173 mil) tssop s2 s1 s0 multiplier 000 x1 001 x2 010 x3 011 x4 100 x5 101 x6 110 x8 111 x16 pin number pin name pin type pin description 1 x1 xi crystal or clock input. connect to a 10-27 mhz fundamental parallel mode crystal or clock input. 2 - 4 vdd power connect to +3.3 v. 5 gnd power connect to ground. 6 vdd power connect to +3.3 v. 7 - 8 gnd power connect to ground. 9 s2 input select pin 2. internal pull-up resistor. 10 s1 input select pin 1. internal pull-up resistor. 11 s0 input select pin 0. internal pull-up resistor. 12 vdd power connect to +3.3 v. 13 nclk output inverted differential clock output. 14 clk output differential clock output. 15 gnd power connect to ground. 16 x2 xo crystal connection. connect to 10-27mhz fundamental parallel mode crystal or leave unconnected for clock input.
ics601-21 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 3 ics601-21 rev i 031306 external components the ics601-21 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01 f and 0.1 f should be connected between vdd and gnd, as close to the part as possible. a 50 ? terminating resistor should be used on each clock output. (see termination diagram on page 5). the crystal must be connected as close to the chip as possible. the crystal should be fundamental mode, parallel resonant. do not use third overtone. for exact tuning when using a crystal, capacitors should be connected from pins x1 to ground and x2 to ground. in general, the value of these capacitors is given by the following equation, where cl is the crystal load capacitance: crystal caps (pf) = (cl-5) x 2. so for a crystal with 16 pf load capacitance, two 22 pf caps can be used. for any given board layout, ics can measure the board capacitance and recommend the exact capacitance value to use. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics601-21. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3 v 10% , ambient temperature 0 to +70 c item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature, commercial version 0 to +70 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.0 +3.6 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.6 v input high voltage v ih x1/iclk pin only vdd/2+1 v input low voltage v il x1/iclk pin only vdd/2-1 v
ics601-21 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 4 ics601-21 rev i 031306 dc electrical characteristics (continued) note 1: outputs terminated with 50 ? to vdd-2v ac electrical characteristics vdd = 3.3 v 10% , ambient temperature 0 to +70 c note 2: input frequency limited by maximum output frequency and multiplication factor (i.e. for 16x, maximum input frequency is 13.75 mhz). parameter symbol conditions min. typ. max. units input high voltage v ih input select pins 2 vdd v input low voltage v il input select pins 0.8 v output high voltage v oh note 1 vdd-1.4 vdd-1.0 v output low voltage v ol note 1 vdd-2.0 vdd-1.7 v output voltage swing v swing peak to peak 0.6 0.95 v operating supply current idd note 1, 125 mhz 30 45 ma input capacitance c in input select pins 5 pf on chip pull-up resistor r pu input select pins 510 k ? parameter symbol conditions min. typ. max. units crystal input frequency fin note 2 10 27 mhz output frequency 10 220 mhz output rise time t or 20% to 80%, no load 600 900 ps output fall time t of 80% to 20%, no load 900 1200 ps output clock duty cycle at vdd/2 45 50 55 % maximum absolute jitter, short term, 125 mhz no load 50 75 ps maximum jitter, one sigma, 125 mhz (x5) no load 12 20 ps phase noise, relative to carrier, 125 mhz (x5) 100 hz offset -90 -94 dbc/hz phase noise, relative to carrier, 125 mhz (x5) 1 khz -116 -120 dbc/hz phase noise, relative to carrier, 125 mhz (x5) 10 khz offset -118 -122 dbc/hz phase noise, relative to carrier, 125 mhz (x5) 100 khz offset -115 -119 dbc/hz
ics601-21 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 5 ics601-21 rev i 031306 parameter measurement information period jitter v oh v ol v ref histogram mean period (first edge after trigger) 1s contains 68.26% of all measurements 2s contains 95.4% of all measurements 3s contains 99.73% of all measurements 4s contains 99.99366% of all measurements 6s contains (100-1.973x10 -7 )% of all measurements reference point clock outputs 80% 80% 20% 20% t or t of o utput r ise /f all t ime v swing 3.3v output load ac test circuit lvpecl v dd = 3.3v gnd =0v scope 50 ? 50 ? z = 50 ? z = 50 ? qx nqx cycle-to-cycle jitter t jit(cc) = t cycle(n) - t cycle(n+1) t cycle(n) t cycle(n+1) nfout fout 1000 cycles 3.3v lvpecl driver termination lvpecl v dd = 3.3v gnd =0v 50 ? 50 ? z = 50 ? z = 50 ? qx nqx v dd -2v = 1.3v pulse width t period o utput d uty c ycle and t period t pw t period odc = nfout fout
ics601-21 low phase noise clock mult iplier clock multiplier idt? / ics? low phase noise clock multiplier 6 ics601-21 rev i 031306 package outline and package dimensions (16-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integr ated circuit systems (ics) ass umes no responsibility for either its use or for the infringement of any patents or other ri ghts of third parties, which would result from its use. no oth er circuits, patents, or licenses are implied. this product is intended for use in normal commercial appl ications. any other applications such as those requiring ext ended temperature range, high reliability, or other extraordinary environmental requirements are not recommen ded without additional pr ocessing by ics. i cs reserves the right to change any circuitry or specificat ions without notice. ics does not authorize or warrant any ics product for use in life suppor t devices or critical medical instruments. part / order number marking shipping packaging package temperature 601G-21 ics601G-21 tubes 16-pin tssop 0 to +70 c 601G-21t ics601G-21 tape and reel 16-pin tssop 0 to +70 c 601G-21lf 601G-21lf tubes 16-pin tssop 0 to +70 c 601G-21lft 601G-21lf tape and reel 16-pin tssop 0 to +70 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
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